Cardinal NIC and Chip Multiprocessor

This repository contains all major projects completed as part of the EECS 4612: Digital VLSI Design course at York University. The projects showcase the complete ASIC design flow — from RTL design to GDSII layout — using industry-grade tools like Cadence Genus, Innovus, and Virtuoso.

DLX microprocessor described in VHDL for the Microelectronic Systems course @ Politecnico di Torino

An application using Cadence IC Package

This repository presents a complete RTL-to-GDSII ASIC implementation of the PicoRV32 RISC-V processor using the Skywater 130nm (Sky130) open-source PDK. The project demonstrates an industry-standard VLSI backend flow using Cadence EDA tools, covering synthesis, placement, routing, verification, and GDSII generation.

This repository is about the main project of the course "VLSI System Design". This course is part of my undergraduate studies on University of Thessally - ECE Department located in Volos, Greece.

ASIC design flow implementation for digital circuits, RTL simulation to physical design using Cadence tools.

Parameterized N×N output-stationary systolic array accelerator for INT8 neural network inference. Full RTL-to-GDS flow on ASAP7 7nm using Cadence Genus + Innovus. 667 MHz, 42.7 GOPS peak throughput, 0.33 mW/GOP. SystemVerilog RTL, synthesis, place-and-route and self-checking testbench included.

SystemVerilog ASIC Portfolio: RISC-V SoC Integration, UVM Verification, AI Accelerators & DSP. Full Flow from RTL to GDSII (Cadence).

Simulation, Logical and Physical Syntesis of the RISC-V Steel Core using Cadence EDA tools.

Detailed routed RT01 and other testcases with Innovus NanoRoute; includes RT01 random blockages. Example routes include CLK paths avoiding all blockages and connecting all DFF pins. All modules are designed with the GSCLK45nm standard cell library. Note that NanoRoute is typically used for routing std cell placements; in this case, custom top-level

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A synthesizable SPI Master–Slave full-duplex communication module implemented in Verilog HDL. This repository covers the complete RTL-to-GDS flow using Cadence tools, including RTL design, verification, synthesis, place-and-route, and timing analysis.

A complete ASIC design flow for a dedicated MNIST Neural Processing Unit (NPU). Features a quantized hardware-friendly architecture, SystemVerilog RTL implementation, and a verified backend-ready flow for logic synthesis and GDSII generation.