Extract embedded ICC color profiles from files

End-to-end RTL to GDSII ASIC physical design implementation at 28nm using Synopsys DC and ICC2 with full timing closure and DRC clean signoff.

An RTL-to-GDSII ASIC Flow Project Design, simulate, synthesize, and layout a full 1×8 demux for 8-bit data — all the way from Verilog to GDSII.