Haskell to VHDL/Verilog/SystemVerilog compiler

Hardware Description Languages

A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.

一篇全面的 Bluespec SystemVerilog (BSV) 中文教程，介绍了BSV的调度、FIFO数据流、多态等高级特性，展示了BSV相比于传统Verilog开发的优势。

Implementation of a Tensor Processing Unit for embedded systems and the IoT.

SystemRDL 2.0 language compiler front-end

Fearless hardware design

Control and status register code generator toolchain

A core language for rule-based hardware design 🦑

A Platform for High-Level Parametric Hardware Specification and its Modular Verification

ACT hardware description language and core tools.

A new Hardware Design Language that keeps you in the driver's seat

Using HDL, from Boolean algebra and elementary logic gates to building a Central Processing Unit, a memory system, and a hardware platform, leading up to a 16-bit general-purpose computer. Then, implementing the modern software hierarchy designed to enable the translation and execution of object-based, high-level languages on a bare-bone computer hardware platform; Including Virtual machine,Compiler and Operating system.

VHDL Guide

A place to keep my synthesizable verilog examples.

A minimalist HDL built entirely from logic gates for education and experimentation. Compiles circuits to C so that they can run anywhere

design and verification of asynchronous circuits

Dadda multiplier(8*8, 16*16, 32*32) in Verilog HDL.

Design and documentation for a very simple 4-bit processor named NibbleBuddy and its assembler.

🔁 elastic circuit toolchain

📚Repositório da Disciplina INE5406 - Sistemas Digitais

5 Day TCL begginer to advanced training workshop by VSD

An experimental package manager and development tool for Hardware Description Languages (HDL).

high abstraction synthesis

YieldFSM, a DSL for describing finite state machines in Clash

This is a personal project which purpose is to learn computer architecture by implementing the Hack Computer.

Given A and B are 64-bit inputs. With two selection lines s1 and s0 to perform the operations, A+B, A-B, AB, C+AB using Baugh Wooley multiplier

Library code for upcoming RetroClash book

A simple tool that can be used to convert the header syntax of a verilog module or VHDL entity to an instantiation syntax and create testbench structures (top level and verify). The project is aimed at removing the need for tedious refactoring of module headers when instantiating modules or verifying individual modules with testbenches.

A RISC-V Single Cycle Processor which is done in verilog.