ASIC design flow implementation for digital circuits, RTL simulation to physical design using Cadence tools.

VHDL implementation of a PS/2 mouse driver with FSM design. Reads 33-bit frames (PS/2 protocol), X/Y motion, overflow, sign, and parity errors. Includes error handling, testbench, synthesis scripts, and timing/power/area reports.

VHDL implementation of a synchronous FIFO (First In First Out) with 64 positions of 8-bit words. Includes status signals (empty, full, almost empty/full, error), asynchronous reset, edge-sensitive read/write, testbench, synthesis scripts, and timing/power/area reports.

SystemVerilog ASIC Portfolio: RISC-V SoC Integration, UVM Verification, AI Accelerators & DSP. Full Flow from RTL to GDSII (Cadence).

VHDL implementation of a UART receiver module using FSM. Supports 8-bit data reception, baud rate selection (9600–57600 bps), parallel output with enable, 100 MHz clock, and parity check. Synthesized and analyzed using Cadence Genus, with testbench, timing, power, and area reports.

VHDL implementation of a UART transmitter module developed for the Integrated Systems Design II course (PUCRS). Includes 8-bit parallel-to-serial conversion, FSM control, baud rate selection (9600–57600 bps), synthesis scripts, testbench, and timing/power/area reports.

A synthesizable SPI Master–Slave full-duplex communication module implemented in Verilog HDL. This repository covers the complete RTL-to-GDS flow using Cadence tools, including RTL design, verification, synthesis, place-and-route, and timing analysis.