Dadda multiplier(8*8, 16*16, 32*32) in Verilog HDL.

simple verilog digital circuits sampels (halfAdder, fullAdder, ALSU , ...)

A 32-bit Kogge-Stone Adder is implemented in this design.

This project was performed on the completion of our B. Tech 4th Semester Summer Training cum Academic Internship Programme on "RISC-V based 32-bit Digital Processor Design using SPICE" under E&ICT Academy IIT Guwahati and Assam Science & Technology University, Guwahati under TEQIP III in association with VLSI Expert

These are VHDL codes for a signed 4bit multiplier using 4bit adders. Base on Baugh-Wooley Method.

LTSpice simulation software is used to study the behavior of a Memristor. Different logic gates like NOR, NAND and XOR were modelled and simulated followed by the simulation of a memristor based full-adder.

This is a VHDL code for 4bit multiplier using 4bit full adder circuit structurally modelled.

A DIY 8 Bit Adder from single transistors

Digital Logic Design using pen and paper to design with Analog discovery 2, and using Verilog for synthesizing. these are some of my junior year labs for Digital Electronics

4-bit Serial Adder/Subtractor with Parallel Load

4 bit ALU in verilog

A project that simulate the circuits FullAdder and FullSubtractor

Digital Design using Verilog

No description provided.

one cycle unsigned multiplier, don't cares of resources fpga or asic structures

No description provided.

➕➕ Arithmetic operations in most machines are performed in the ALU whereby logic gates and flipflops are combined so that they can subtract, multiply, and divide binary numbers. This circuit only implements the addition part, on four bit digits

Simulation of full adder circuit to add two byte-sized integers in Python 3.

The computational speed of the dadda multiplier can be enhanced by partitioning the partial products. In process to achieve low power we have considered pass transistor for logical implementation.

Learned as a part of CS210 course

A collection of Verilog code examples, perfect for beginners or anyone looking to learn Verilog. These examples are based on my homework assignments from my university and include comments and explanations to help you understand the code better. Check out the link below for more information about Verilog!! 👇

VHDL homework from FH Technikum Wien Master Embedded Systems course VHDL

This project is a 32-bit Arithmetic Logic Unit (ALU) designed in SystemVerilog as part of a MIPS microprocessor simulation. The ALU supports various arithmetic and logical operations and includes a custom-built 32-bit full adder, one 2-to-1 MUX, one 4-to-1 MUX, one AND gate , one OR gate and the Zero Extend Logic

RTL implementation of a 1-bit Full Adder using Verilog HDL with functional verification through simulation.

Some basic VHDL projects.

porject from designing with VHDL course. Includes, FSM (finite state machine), next state logic,seven-segment-display-decode, full adder, flip flops, D_flip-flops, ripple carry adder, full adder, half adder, delay propagation

➕➖ Arithmetic operations in most machines are performed in the ALU whereby logic gates and flipflops are combined so that they can subtract, multiply, and divide binary numbers. This circuit only implements the addition part and subtraction on four bit digits

Some logic circuits for studies and reviews

An 8-bit array multiplier is a combinational circuit that multiplies two 8-bit binary numbers using a grid of AND gates for partial product generation and full/half adders for their parallel addition. It offers high-speed operation through simultaneous processing, structured in a regular, hardware-efficient layout.

from back in the university, a digital design laboratory project adding 2 number of 3 bits