React.js + Three.js 3d room planner & product configurator(bundled version)

React.js + Three.js 3d room planner

[FPGA 2023] FADO: Floorplan-Aware Directive Optimization for High-Level Synthesis Designs on Multi-Die FPGAs

Synthesis using Synopsys DC and Physical Design flow using Synopsys ICC II, of my RISC-V 5 stage pipelined using 32 nm tech repo

This is the official repository for the survey paper titled as "A State-of-Art Survey on Generative AI Techniques for Floor Planning"

Python parser for MCNC benchmark netlists

An algorithm collection for 2-dimensional floorplanning using strip packing (Min. H, given fixed W)

This VirtualRoom Planner is a user-friendly web-based application that allows users to design their room layout in both 2D and 3D environments with Virtual Reality (VR) support. Currently available for desktop (PC/Laptop) only.

Physical design flow of the PicoRV32 processor using Cadence Genus and Innovus

An application using Cadence IC Package

Fall 2024 NYCU Physical Design Automation (PDA)

A Universe of Floor Plan Possibilities

NYCU Physical Design Automation

End-to-end RTL to GDSII ASIC physical design implementation at 28nm using Synopsys DC and ICC2 with full timing closure and DRC clean signoff.

Employs a Mixed Integer Linear Programming technique to optimize the floorplan of a VLSI chip using Python

Employs a Mixed Integer Linear Programming technique to optimize the floorplan of a VLSI chip using C++.

An RTL-to-GDSII ASIC Flow Project Design, simulate, synthesize, and layout a full 1×8 demux for 8-bit data — all the way from Verilog to GDSII.