A PyTorch library for all things Reinforcement Learning (RL) for Combinatorial Optimization (CO)

A High-performance Timing Analysis Tool for VLSI Systems

ASIC implementation flow infrastructure, successor to OpenLane

[NeurIPS 2024] ReEvo: Large Language Models as Hyper-Heuristics with Reflective Evolution

CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture

GDSII File Parsing, IC Layout Analysis, and Parameter Extraction

FAN (fan-out-oriented) ATPG (Automatic Test Pattern Generation) and Fault Simulation command line tool

A flexible framework for analyzing and transforming FPGA netlists. Official repository.

A Standalone Structural Verilog Parser

A powerful Python framework for orchestrating AI agents and managing complex LLM-driven tasks with ease.

VLSI EDA Global Router

EDAV: Open-Source EDA Viewer; render design LEF/DEF files in your browser!

A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SPEF).

RL_PCB is a novel learning-based method for optimising the placement of circuit components on a Printed Circuit Board (PCB).

design and verification of asynchronous circuits

A standalone structural (gate-level) verilog parser

Hop-Wise Graph Attention for Scalable and Generalizable Learning on Circuits

This is a deep-learning based model for Electronic Design Automation(EDA), predicting the IR drop location on the chip.

🤖 Intelligent AI-powered PCB design automation tool using machine learning for component placement, routing optimization, and signal integrity analysis. Supports KiCad, Altium Designer, and Eagle CAD integration.

Awesome machine learning for logic synthesis

Selected problems and their solutions from the book on "Machine Intelligence in Design Automation"

the awesome work, project and lab of EDA (Electronic Design Automation). continue update...

AIM: Accelerating Arbitrary-precision Integer Multiplication on Heterogeneous Reconfigurable Computing Platform Versal ACAP (Full Paper accepted to ICCAD2023)!

This is a deep-learning based model for Electronic Design Automation(EDA), predicting the congestion location.

Nix flake for more up-to-date versions of EDA tools

EDA Analytics Central

Incremental Timing-Driven Placement, problem C of ICCAD contest 2015

Source code for the Paper: "Deep Reinforcement Learning for Analog Circuit Sizing with an Electrical Design Space and Sparse Rewards"

Technology file parser in Rust

This is a deep-learning based model for Electronic Design Automation(EDA), predicting the Design Rule Check (DRC) violation location.