"100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado

All my projects, homework, hand writings, course slides and anything I have learned and done during my studies at IUT😊. feel free to give it a ⭐=)

Fixed Point FPGA-based Hardware Implementation of a 32-tap Low Pass FIR Filter for Audio Applications

CSC302: Digital Logic Design and Analysis [DLDA] & CSL301: Digital System Lab [DS Lab] | SE Semester III | Computer Engineering

Implementation of a low-pass FIR filter in Verilog HDL.

My activity in digital systems

Implementation and verification of a hardware-based controller for a three-phase induction motor on an FPGA — Bachelor's Thesis [UPC-TTU, 2019]

Direct Digital Synthesizer for Generating Sine Waves using Verilog HDL

3-stage RISC-V Pipelined Processor with interrupt CSR support

Digital Systems Design - Spring 2023 - Sharif University of Technology

Implementation of a FIFO structure for Digital Systems | Written in Verilog HDL

Verilog implementation of the basic structure of an FPGA

This GitHub repository Consists of materials, code samples, documentation, and valuable resources related to the Information Technology (IT) Department at the National Institute of Technology Karnataka (NITK). 📚 Resource Library 💻 Code Samples 🗂️ Project Repositories

Repositorio con las 12 prácticas en VHDL para el curso impartido por la profesora Nayeli Vega, tomada en la ESCOM, IPN.

FIFO Buffer Implemented in VHDL

Lab projects using Verilog HDL

Digital Logic Design (DLD) is a fundamental subject for the engineering students worldwide. Well, many students find it difficult to design the digital circuits properly while pursuing the DLD course in colleges or universities. Therefore, I will try to assist those students by sharing my lab works with them.

Binary Adder, Subtractor, Multiplier, Divider in VHDL with FPGA board.

Digital System Design Course (1st year, 2nd Semester)

This is a simple project that shows how to multiply two 8x8 matrixes in Verilog.

Home automation simulation project created for the UofT ECE241 course. Worked on by Harsh Grover and Joonseo Park. More details in README

Digital Systems Design With VHDL laboratory sessions, Fall 2018

Term project and lab assignments for CS303 - Logic and Digital System course in Sabancı University, Fall 2021-2022.

Very basic computer created in Logisim Evolution. Just to show off your computer architecture skills.

Digital System Design Verilog Implementation

The ALU is a crucial component of digital systems, responsible for executing arithmetic and logical operations. This project is an RTL design of 16 bit ALU using verilog.

Contains my resume

Academic Lab Course of the 27th batch of Computer Science & Engineering | University of Rajshahi - 🇧🇩

:space_invader: My studies with Verilog and notions of digital systems.

personal files for courses I took at Technical University of Cluj-Napoca