180 results for “topic:digital-logic-design”
Digital logic design tool and simulator
An HDL embedded in Rust.
30 Days of Verilog: Dive into digital circuits with a month of Verilog coding challenges. From logic gates to FSMs, sharpen your skills and simulate your designs. Let's code and conquer circuits!
Oombak 🌊 is an interactive SystemVerilog simulator UI that runs on your terminal!
FAST NUCES Karachi - BSCS Second Semester Repository | Access notes, assignments, past papers, & more. For queries or suggestions, contact k232001@nu.edu.pk.
Composable digital logic simulation in Rust!
A Python-based HDL and framework for silicon-based witchcraft
透過數位邏輯結合VHDL與Verilog的過程，作為從基礎數位邏輯到計算機系統結構，並實作出一顆CPU的教學書籍，希望未來可以成為教學範例檔案。目前將開發轉移到GitLab，因為可以呈現數學與MUL圖。
CSC302: Digital Logic Design and Analysis [DLDA] & CSL301: Digital System Lab [DS Lab] | SE Semester III | Computer Engineering
BUPT 数字逻辑与数字系统课程设计项目
Digital Logic Gate Simulator powered by React and WebGPU
This repository contains all major projects completed as part of the EECS 4612: Digital VLSI Design course at York University. The projects showcase the complete ASIC design flow — from RTL design to GDSII layout — using industry-grade tools like Cadence Genus, Innovus, and Virtuoso.
🎓💻All of my projects at University of Tehran
🚗 A Car Parking Simulator made in LogicWorks 5 as a final project for the course "Digital Logic Design (EE227)"
VLSI Design - Autumn Semester 2022 - Indian Institute of Technology Bombay
VHDL codes for UART Interface; hardware communication protocol. contains Receiver & Transmitter units & RAM memory.
Python digital logic library
This repository contains my work in completing the course titled "Building a RISC-V CPU Core" offered by the Linux Foundation through edX.
BS AI FAST NUCES Coursework material from 2022 - 2026. Access Course Outlines, Books, and Slides with ease.
A library of useful, fully parameterized RTL designs implemented in SystemVerilog.
My second semester project for my object-oriented programming course. A simulation game for the lab work done in my second semester Digital Logic Design course.
CSE 1003 Digital Logic And Design's Lab Components all packed up in one neat and arranged repository
DLD Project - A simple vending machine simulation with Verilog (Spring 2024)
32-bit Divider circuit implemented using Verilog
Clock and UART Baud rate generation, radix-4 multiplier, function generator & accelerator wrappers.
This repository contains information about Digital Logic Design (ecen 3233) laboratory elements for Fall 2023.
VHDL Code for Labs done in a 2nd year engineering Digital Systems course (ELEC 271) at Queen's University.
This is a 8 bit binary number multiplier using wallace tree.
基于Nexys4开发板和PS2通信协议的键盘设计的电子琴，能够支持24个音阶的弹奏。
⚡ A collection of Digital Logic Design (DLD) lab work and projects 🔌. Includes circuit designs, truth tables, simulations, and practical implementations. Covers core concepts of logic gates, combinational & sequential circuits, and hands-on problem-solving in digital systems.