Digital logic design tool and simulator

Teaching-focused digital circuit simulator

Here are my GATE CSE 2021 Resources

IceChips is a library of all common discrete logic devices in Verilog

here the notes provided by the seniors who already cracked IITs as well as how much I'll cover for my exams I'll provide my notes as well. If you want you can access the course by these links also

A digital logic simulator inspired by Logisim.

8-bit combinational ALU built from scratch with 3,488 CMOS transistors (KiCad + SPICE + Logisim + 1.24M tests

A simple 8 bit UART implementation in Verilog, with tests and timing diagrams

Simple Java application for simulating digital circuits

Labs for computer science: C, assembly, data structure, CSAPP, HSI, Matlab, digital logic, Verilog, compilers, operating systems

Connection Machine is an open-source desktop application for designing and simulating digital circuits at scale.

VHDL code examples for a digital design course

32bit Simplifier of Boolean functions

透過數位邏輯結合VHDL與Verilog的過程，作為從基礎數位邏輯到計算機系統結構，並實作出一顆CPU的教學書籍，希望未來可以成為教學範例檔案。目前將開發轉移到GitLab，因為可以呈現數學與MUL圖。

Project implementations for the NAND2Tetris (Elements of Computing Systems) course, building a complete computer system from NAND gates to a functional CPU using HDL and low-level system design.

This is the mirror for gitee in github for project assignment of cs202 / 214 Computer Organization course of Southern University of Science and Technology， which is to manufacture a CPU. 这是南方科技大学CS202/214计算机组成原理课程的大作业——实现一个CPU。

An experimental package manager and development tool for Hardware Description Languages (HDL).

Compiling finite generators to digital logic. WIP

WIP open source tooling for the XC9500 / XC9500XL series of CPLDs from Xilinx.

A powerful tool for minimizing Boolean functions

Undergraduate Courses in Computer Science at SUSTech

The design and implementation of simple computer by quartus.

Formal verification engine for Verilog with built-in support for simulating flip-flop metastability

This repository contains the codes for various type of circuits simulated in VHDL in Xilinx ISE Design.

Simulating hand drawn digital-logic circuit diagrams projected onto a sheet of paper!

Binary adder implementation in the Game of Life written in JavaScript using canvas.

Tool for creating synchronous models and behavioral specifications for asynchronous circuits

北邮数字逻辑课程设计之电子钟

Python digital logic library

The Karnaugh Map (KMap) Solver is a C++ application featuring a graphical interface for solving Karnaugh Maps. Users can interactively input values into a KMap grid and calculate corresponding minterms. The project aims to simplify Boolean expressions and visualize them using logic gates.