📚 📖 📚CSE GATE Resources for GATE and CSE Aspirants 😎 😁 . Show your ❤️ by ⭐️⭐️

Teaching Materials for Dr. Waleed A. Yousef

ASIC implementation flow infrastructure, successor to OpenLane

This repository hosts the code for an FPGA based accelerator for convolutional neural networks

Python script for generating lookup tables for the gm/ID design methodology and much more ...

A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.

Open-source FPGA development board for education and digital design learning. Focused on accessibility, reproducible hardware and open toolchain integration for students, makers and academic environments.

Introduction to FPGA emulation and digital design. This capstone project was part of the 2021 University of San Diego Shiley-Marcos School of Engineering & Computing Showcase.

Comprehensive verification suite for the AHB2APB Bridge design, featuring SystemVerilog and UVM-based methodologies. 🌉🚀

An open source, parameterized SystemVerilog digital hardware IP library

From Kernel-Level Parallel Programming to Custom AI Inference Accelerator Design — powered by NVIDIA GPUs, Jetson, and tinygrad

VHDL code examples for a digital design course

AdobeAllInOne is a comprehensive suite of creative software tools developed by Adobe. It includes a range of applications for design, photography, video editing, and more, making it the ultimate solution for all your creative needs.

北京邮电大学 2023-2024 春季学期《数字逻辑与数字系统课程设计》——电子钟、药片装瓶系统和贪吃蛇

The project uses a Xilinx Artix-7 FPGA on a Digilent Basys 3 board to design a clock whose seconds, minutes, & hours are displayed on a Quad 7-segment display & can also be displayed on a vga display. Picoblaze processor is used to control the Analog & Digital displays of the clock.

Minimalistic RV32I RISC-V Processor in System Verilog

Solutions for The Nand Game, a game that teaches the fundamentals of computing by building a computer from scratch.

32 bit pipelined binary floating point adder using IEEE-754 Single Precision Format in Verilog

A repository containing the source codes for the Digital Design and Computer Organization Laboratory course (UE18CS2) at PES University.

A collection of my cources, lectures, articles and presentations

Distributed arithmetic (DA) is another way of implementing a dot product where one of the arrays has constant elements. The DA can be effectively used to implement FIR, IIR and FFT type.The DA logic replaces the MAC operation of convolution summation o into a bit-serial look-up table read and addition operation .

A VHDL-based VGA driver to display 256 different colors on a monitor.

An introduction to integrated circuit design with Verilog and the Papilio Pro development board.

Router 1 x 3 verilog implementation

A minimalistic single-cycle RISC-V platform for demonstrational and educational purposes in Logisim Evolution.

USAGI is a Python script designed to automate the process of synthesizing and performing gate-level simulations for digital designs across a range of cycle times.

An experimental package manager and development tool for Hardware Description Languages (HDL).

This Repository contains the Implementation of the AMBA APB4 Protocol with Verilog, featuring an APB master, APB slave with cache memory, and comprehensive testbenches. Includes scripts for fast simulation and synthesis using QuestaSim, Vivado and Quartus Prime

My very own CPU architecture! Emulator availible!

SystemVerilog examples for a digital design course