Digital logic design tool and simulator

A digital logic designer and circuit simulator.

CircuitVerse Primary Code Base

A free, open source, online digital circuit/logic designer.

Basic electrical simulation software with easy UI

API of homomorphic binary operations such as binary comparisons or binary divisions using the library HElib

Simulation of Ben Eater's 8 bit computer running in the logic simulator called Digital

Fritzing parts for most common DIP ICs including 74LS Series and more, which is used in Digital Electronics or Logic Circuit and Design.

Tydi: an open specification for complex data structures over hardware streams

Describing RTL circuit in Ruby

✨ A CS Beginner's Blog

Educational software for modelling and simulation of digital circuits.

A visual and constructive framework for teaching digital circuits.

MapBuf: Simultaneous Technology Mapping and Buffer Insertion for HLS Performance Optimization

Методичка по высшей цифровой схемотехнике + Verilog

Simple 6502 / 65C02 implementation

Generate ATPG for fault detection on Verilog circuits. C++/QT

A custom campaign adding a GPU to the game Turing Complete

Module-level circuit diagram drawing tool 模块级电路图绘制

Windows application for designing and simulating digital logic circuits, written in C++ using CMU graphics library.

Lectures on Digital Design

Slides for my talk at ACT 2022, 'Fully abstract categorical semantics for digital circuits'

Motorcycle LCD Digital Speedometer Odometer

Extended abstract for my SYCO 8 talk, 'Normalisation by evaluation for digital circuits'

This project simulates a 555 timer generating clock pulses for a 4017 decade counter using object-oriented programming with C++

Sem-wise note for the courses offered to CSAM branch in IIITD

Smorgasbord of HDL codes

Generates the Latex Code for the Boolean Function

Arquitetura e Organização de Computadores DCC301: Avaliação de Barramento

This project implements a single-port RAM using Verilog. The design simulates a memory module with a single read/write port, supporting basic memory operations like data storage and retrieval. It includes testbenches for functional verification and timing analysis to ensure reliable operation.