Pong game on FPGA Max 10 DE10-Lite, written in VHDL.

The Design and Implementation of an Autonomous Mars Rover that has full mapping, remote control and power management capabilities.

ECE 385 Final Project -- Ethernet on MAX10 DE10-Lite FPGA and Nios II soft processor

Simple verilog project with ability to connect to GPS module using UART and parse NMEA coordinates using finite state machine

This repository showcases the projects I developed for the DE10-Lite board as part of the "FPGA Capstone: Building FPGA Projects" course on Coursera.

VGA demo on the Terasic DE10-Lite FPGA board

No description provided.

VHDL implementation of the Defender arcade game for DE-10 Lite FPGA. For ECE 4110 project.

ieee_proposed with names changed to floatfixlib to be compatible with Quartus Prime Lite and support fixed, float, etc.

Simulation platform that enables VHDL-style C++ coding. VCD generation for easy debug. VHDL code generation using C preprocessor. Simple risc-V rv32i SoC example, + Risc-V test suite and gcc bare-metal example. Linux (or WSL) / clang or gcc / risc-v toolchain / quartus required

ADC demo on the Terasic DE10-Lite board with MAX10 FPGA

Welcome to the BitBlaster_10bit_Processor! Our custom-designed 10-bit processor, crafted meticulously as part of a project for a Digital Logic Design course at South Dakota State University.

This is a template for projects using the Quartus Prime suite with the DE10-Lite FPGA board.

This repository showcases a Verilog-based Snake and Apple Game, developed for the ECL 106: Digital System Design with HDL course. Running on an Altera DE10-Lite FPGA board and displayed on a VGA monitor, players control a snake to collect apples while avoiding obstacles. The snake grows longer with each apple, making the game progressively harder.

A recreation of the popular game Tic-Tac-Toe for the DE10-Lite FPGA dev board, in VHDL.

Train ticket vending machine application designed for execution on an FPGA system. The application allows users to purchase tickets for various destinations and includes maintenance functionalities.

Nios II Embedded System Dhrystone Test

Terasic Servo Motor Kit (SMK) usage examples

Using the DE10 Lite board, read an analogue signal (512 samples) and send the data out of a UART

A Reaction Timer for the DE10 Lite FPGA Written in Verilog HDL

VHDL Project 2018-2019: A university project to discover VHDL and the DE10 LITE 10M50DAF484C7G, just a "Moving Light Emitting Diode". The changing LED states between 10 LEDS creating the illusion that one LED is moving.

Transferring data from SPI to UART using BMP280 sensor with Verilog

KelvinThomasYB17/VGA-Radar-sensor-using-VHDL-and-NIOS II

Design of a Simple CPU using the DE10-Lite FPGA from Intel and Quartus Prime

This is a Pong Game created by Group 22 for EEE308 project, Electronics and Electrical Department, Obafemi Awolowo University.

A A collection of Verilog/SystemVerilog projects developed for the DE10-Lite FPGA board using Intel Quartus.

Hello World from Nios 2

No description provided.

Traffic Light System with VHDL

This repository contains the implementation of a motor speed control system using an FPGA. The speed is adjusted dynamically through a potentiometer, leveraging ADC for analog-to-digital conversion and PWM for precise motor control.