DE1SOC DE10-NANO DE10-Standard OpenCL hardware that support VGA and desktop. And Some applications such as usb camera YUYV to RGB , Sobel and so on.

Reconstructing NES game console on Altera DE1-SOC FPGA using System Verilog

Yet Another Tetris on FPGA Implementation

A multiple interface (intel 8080, 3-wire SPI, DPI RGB ) 5 inch TFT LCD capacitive touch screen which is compatible with teraisc DE-series boards

Audio Signal Processing SoC

A neural network built in Verilog for the DE1-SoC FPGA board for handwritten digit recognition.

Connect a modern, high-resolution camera to an FPGA and easily develop your applications

FPGA Verilog HDL design project (DE1-SoC)

Division Algorithms in FPGAs

Audio Signal Processing SoC Project Website

🔧 University of Toronto ECE243 Final Open software project.

CSEE 4840 Embedded System Design Project - Hardware (Sound Localizer)

Final project for ECE243

Space Invaders created using C for the De1-SoC board. Made in the winter 2020 semester for the ECE243 class.

Implementation of Hopfield network using Verilog

Network-Controlled LED system on DE1-SoC using TCP/IP, ARM-HPS, and FPGA-based LED control.

FPGA Based Point of Sale Project using Verilog

A language learning solution to learn vocabulary from day-to-day objects with front-end on De1-SoC Cyclone V FPGA and backend on a Raspberry Pi, incorporating Microsoft Azure Cognitive Services

A single-cycle RISC-V processor implemented in SystemVerilog and tested on the DE1-SoC Development Kit

FPGA project using DE1-SoC board that can process images into different filter effects

Real-time trumpet audio enhancement system with note detection, frequency analysis, and live DSP effects implemented across the DE1-SoC’s ARM processor and Cyclone V FPGA.

Waveform generator on DE1-SoC FPGA - sine/PWM waves, 16 frequencies (10Hz-10kHz), TLC7524CN DAC

An absolute pitch testing game developed on DE1-SoC FPGA with multiple difficulty levels and practice mode

No description provided.

This project implements a Rock-Paper-Scissors game on the ARMv7 DE1-SoC platform.

OpenEmbedded/Yocto BSP layer for Altera DE1-SoC

Response-Time Game written in VHDL. Supports cheat-prevention, pseudo-random delay, ws2812b response visualization and custom time-windows.

Tamagotchi Implementation in VHDL

Plasma MIPS (I) SoC

🐸 Frogger-like arcade game written in Verilog for the Altera DE1 FPGA board