34 results for “topic:ddr3”
CoreFreq : CPU monitoring and tuning software designed for the 64-bit processors.
Opensource DDR3 Controller
SPD Reader & Writer with Software Write Protection capabilities supporting Arduino and SMBus
DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow video controller with alpha-blended layers. Docs & TBs included.
A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs
mirror of https://git.elphel.com/Elphel/eddr3
Open hardware compute module with Allwinner A13 (ARM-A8 @1GHz), DDR3 (max 512MB) and expansions (USB, GPIO, WiFi, LCD, Audio)
A RISC-V SBC based around the LambdaConcept USB2Sniffer FPGA board.
在FPGA中将图像数据输入到DDR3中，再输送到HDMI接口上进行显示。
M.2 PCIe Artix 7 FPGA Accelerator Card
4-Layer XC7Z010 DDR3 Layout
Noir Computer
DDR3 controller for nMigen (WIP)
SpaceVNX (VITA 74.4) carrier based on Zynq-7000.
Kopflos Computer
将图像数据从以太网传输到DDR3，再传输到HDMI进行显示的vivado例程
Demo board for the i.MX6ULL Single-Core Processor with Arm Cortex-A7 Core
A curated list of awesome Rowhammer papers, tools, and info resources. 👉 Content coming soon, stay tuned!
A simple command line tool for reading and writing AT24/EE1004 SPD EEPROMs.
RISC-V based SOC for Qmtech Artix7-100 Wukong board with 720p VGA, DDR3 and cache controller
Device trees for TF-A, OP-TEE, U-Boot, Linux working boot chain
Artix 7 Parallel OV5640
Python CLI for decoding, analyzing, diffing, and patching DDR SPD EEPROM data (DDR2/DDR3/DDR4) with JEDEC, XMP, and SmartMemory support.
Artix-7-Parallel-OV2640
Artix-7-Parallel-OV9655
Artix-7-Parallel-OV7670
A Lite DRAM helper maked in System Verilog HDL.
Test SBC with Allwinner A13
Artix-7-Parallel-OV7740
An attempt at making a 2-way superscalar out-of-order riscv processor for an Arty s25 fpga.