Nand2Tetris: Build a computer system from the ground up, from nand to tetris. Hardware and software.

MIT Course 6.004 - Computation Structures

Materials for the Computer Science course, Digital Design (Logic Circuits)

A 32-bit ALU using combinational logic written in Verilog.

An efficient combinatorics library for JavaScript to generate and get the list of all Permutations and Combinations with the ability to enable or disable repetition. (utilizing ES2015 generators)

This is a Combinational Circuit Logic Simulation Tool. There is a C++ version and a C version.

Design of the implementation of a calculator connected on the integrated FPGA

Simple Kotlin Project Using Kotlin Language

Source code for various Verilog-based projects and assignments

VHDL projects for combinational and sequential logic design on FPGA.

This project implements a 4-bit binary to hexadecimal decoder using basic logic gates, driving a common anode 7-segment display. Designed for simulation in CircuitVerse, it demonstrates practical digital logic design skills for use in embedded systems, control circuits, and digital displays.

simulation of essential combinational logic circuits with boolean algebra

MUX VHDL | Układ kombinacyjny VHDL

This repository contains synthesizable VHDL code for basic combinational logic circuits such as Adder with register, 2:4 decoder, 4:2 priority encoder, Multiplier with register and other circuits.

EE89H Final Project

Codes written by me in my Digital Logic Design course.

Personal coursework for Computer Organization at Northeastern University (2025). Includes digital logic designs, FSM implementations, and a complete MIPS CPU architecture in Logisim.

Analyze the combine with and without the repetition. (SOON)

This script lists out all paths from inputs to outputs of an input combinational circuit in the form of structural/gate-level modelling in verilog. The BFS graph algorithm is used.

These are the assignments of Second year Analog Digital Electronicd subject

VHDL implementations of half-adders, full-adders, and a 4-bit adder for digital circuit design

Designing Single-Cycle Microprocessor without Interlocked Pipeline Stages (MIPS) using Verilog.

4 bit Calculator using Logic Gates

CPEN 211: Computing Systems I

Course summary and comprehensive exercises covering all Computer Systems and Logic topics including boolean algebra, logic circuits, sequential circuits, and advanced digital design.

Circuito combinacional con entrada de 4 bits (número sin signo en binario puro) y salida con un número de 4 bits, su valor es redondear la operación 4 x RAIZ CUADRADA(y) al entero más próximo. El circuito se diseña de diversas maneras, cada una con una descripción en VHDL como arquitectura de la entidad.

Foundational digital logic projects built in Falstad — combinational circuits, sequential systems, and a simple CPU with automated instruction execution.

An 8-bit array multiplier is a combinational circuit that multiplies two 8-bit binary numbers using a grid of AND gates for partial product generation and full/half adders for their parallel addition. It offers high-speed operation through simultaneous processing, structured in a regular, hardware-efficient layout.

Verilog codes related to digital logic design are available

This repository contains the project files and report for an ASCII letter to Morse Code converter built using only basic sequential and combinational logic circuits.