OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.

Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.

Learn, share and collaborate on ASIC design using open tools and technologies

CLEAR is an Open Source FPGA ASIC delivered to you on its development board and its open source software development tools and all the ASIC design tools used to create it.

PLL configuration generator for the Caravel management core

One-button Heroku deploy for the Caravel data exploration platform.

A PCB created for FABulous FPGAs, based on the caravel board.

An example project that utilizes caravel user space for an ibex based SoC

Eight different verilog projects are combined to creat a big custom asic project.

Implementing an AES ecnryption IP Core with Caravel Platform

RISC-V Reference SoC Design and Tapeout Program Phase 2 personal documentation

Implementing an AES ecnryption IP Core with Caravel Platform

This repository contains documentation and relevant materials for the RISC-V SoC Tapeout Program, a collaborative initiative between IIT Gandhinagar, VLSI System Design (VSD), and other prominent organizations in the field of semiconductor design.

An ASIC running Pong.

Druid(v0.8.3) Docker Image(with druid-datasketches extension and caravel included) — Edit