ASIC design flow implementation for digital circuits, RTL simulation to physical design using Cadence tools.

Layered SystemVerilog testbench for verifying a parameterized Synchronous FIFO. Includes directed and constrained-random tests, functional coverage, assertions, and scoreboard-based checking.

SystemVerilog ASIC Portfolio: RISC-V SoC Integration, UVM Verification, AI Accelerators & DSP. Full Flow from RTL to GDSII (Cadence).

Exercícios desenvolvidos durante a disciplina Concepção Estruturada de Circuitos Integrados, relacionando os mais diversos assuntos da mesma.

This project presents the verification of a FIFO design using the UVM.