32-bit Superscalar RISC-V CPU

Go library providing algorithms optimized to leverage the characteristics of modern CPUs

Cycle-accurate pre-silicon simulator of RISC-V and MIPS CPUs

💻 RISC-V Simulator of RV32I ISA. 5-stage pipeline / out-of-order execution with Tomasulo algorithm and Speculation. Support runtime visualization. Project report available.

Advanced Architecture Labs with CVA6

Super scalar Processor design

🎞 Implementation of several Branch Prediction algorithms and analysis on their effectiveness on real-world program traces.

Pathfinder: High-Resolution Control-Flow Attacks Exploiting the Conditional Branch Predictor

Kite: Architecture Simulator for RISC-V Instruction Set

Computer Architecture UIUC SP 2018

A branch predictor simulator in C++ that tests 6 different types of branch predictors.

A MIPS processor with Cache and Advanced Branch Predictor written in SystemVerilog

Computer architecture related projects

Two Level Branch Predictor Simulator - EE382N Superscalar Microprocessor Architecture, Spring 2019, Assignment 4

Tool for visualizing and comparing different dynamic branch prediction methods for a pipelined processor.

VHDL code of three branch predictors

This repository contains the code to benchmark CPU cache miss latency and branch misprediction penalty

System benchmarks over JVM with JMH - SIMD (superscalar processing), Branch prediction, False sharing.

A pipelined implementation of a MIPS processor that was optimized to use data forwarding, caching and branch prediction.

SystemVerilog implementation of RISC-V RV32I_Zmmul & custom packed SIMD ISA as 5-stage single-issue CPU core with branch predictor and L1 caches, tied up in lockstep with ISA sim over DPI for verification

C++ Instruction Set Simulator for RISC-V RV32IMC & custom packed SIMD ISA with cache and branch predictor models, C/ASM workloads, and Python analysis tools

2 bit saturated branch predictor with BHR (Branch History Register)

Branch Predictor is a C# program that runs a gshare branch prediction simulation, according to a specified number of Global Buffer Table (GBT) and Global History Record (GHR) bits. 2019.

A superscalar out-of‐order architectural simulator (With Memory Hierarchy).

Implementation of advanced branch predictors, including Perceptron and Combinational Two-Level Adaptive Predictors, within the SimpleScalar simulator. Showcases enhancements in prediction accuracy and dynamic branch prediction techniques. This is a project for PSU ECE 587: Advanced Computer Architecture

Simple RISC-V assembler program based on Venus that converts RISC-V assembly language (.asm) into machine language (.mc) format.

CENOS: The Modern CPU Simulator

Playing with branch-prediction and simulation

MIPT-V Pipeline Flowchart Visualizer

Implementation and evaluation of multiple branch predictors (Static, N-bit, Gshare, BTB+RAS) using Intel Pin Tool on PARSEC benchmarks. Includes scripts for running simulations and generating MPKI visualizations.