An AXI4 crossbar implementation in SystemVerilog

RISCV CPU implementation in SystemVerilog

This repository contains the implementation of AXI4-Lite interface protocol on system verilog for FPGA/ASIC communication. Modular codebase with example designs and testbench.

Spring 2024 NYCU Integrated Circuit Design Laboratory (ICLAB)

All about FPGA...

This repo contains an implementation of Axi4 lite interface on system verilog. Verilator and Vivado tools are used .

Introduction in Reconfigurable Computing (using reconfigurable Systems-on-Chip rSoC)

SystemVerilog ASIC Portfolio: RISC-V SoC Integration, UVM Verification, AI Accelerators & DSP. Full Flow from RTL to GDSII (Cadence).

In this repository, an AXI4-Lite Protocol Slave Peripheral Transaction has been coded that can receive data packets, validate them based on sorting condition valid or invalid storage. The design of storages is a simple FIFO-like sorting.

SystemVerilog UVM verification IP for an AXI4 memory slave supporting INCR bursts, outstanding transactions, ID-based ordering, write strobes, and protocol SVA assertions.

An FPGA-based temperature processing system on Basys 3 using AXI4-Stream architecture. It captures sensor data via UART, applies a sliding average filter, and tracks real-time Min/Max values.