2 results for “topic:axi4-lite-system-verilog”
This repo contains an implementation of Axi4 lite interface on system verilog. Verilator and Vivado tools are used .
SystemVerilog ASIC Portfolio: RISC-V SoC Integration, UVM Verification, AI Accelerators & DSP. Full Flow from RTL to GDSII (Cadence).