AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

An AXI4 crossbar implementation in SystemVerilog

AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream transmitter and receiver verification components

AXI4 and AXI4-Lite interface definitions

Basic USB 1.1 Host Controller for small FPGAs

Audio controller (I2S, SPDIF, DAC)

USB -> AXI Debug Bridge

HLS for Networks-on-Chip

Interface definitions for VHDL-2019.

Master and Slave made using AMBA AXI4 Lite protocol.

This repository contains the implementation of AXI4-Lite interface protocol on system verilog for FPGA/ASIC communication. Modular codebase with example designs and testbench.

Multi-port BRAM IP for ASIC and FPGA

Formal AXI verification properties from the eXpect framework for secure SoC validation

Axion-HDL: Automated AXI Register Space Generation Tool

VHDL generator from SystemRDL

A tutorial on the usage of AXI4-Lite and AXI4-Stream Interfaces on HW Accelerators generated through High-Level Synthesis (HLS)

A UVM-based verification environment for a multi-core, write-back L2 cache on 32-bit RISC-V, enforcing MESI coherence with L1 caches and interfacing to DRAM over AXI4-Lite.

A collection of formal properties for hardware buses, and cores using them.

This repo contains an implementation of Axi4 lite interface on system verilog. Verilator and Vivado tools are used .

OLED driver demo running on ZedBoard

A Custom AXI4 SPI Peripheral

Introduction in Reconfigurable Computing (using reconfigurable Systems-on-Chip rSoC)

SystemVerilog AXI4-Lite Slave IP with Hazard-Stalled FSM. Verified with 2M+ cycle randomized regression and 'Snoop & Serialize' collision handling.

Popular bus implementations in Verilog HDL

SystemVerilog ASIC Portfolio: RISC-V SoC Integration, UVM Verification, AI Accelerators & DSP. Full Flow from RTL to GDSII (Cadence).

AMD Vivado Demonstrator Design using The PoC Library features.

AXI4-Lite compatible Driver module for use with Verilator and other DPI-C compatible simulators.

In this repository, an AXI4-Lite Protocol Slave Peripheral Transaction has been coded that can receive data packets, validate them based on sorting condition valid or invalid storage. The design of storages is a simple FIFO-like sorting.

A dual-channel, AXI4-Lite controlled Phase Accumulator Waveform Generator IP core for Xilinx Zynq FPGAs, featuring fixed-point DSP math and Linux driver support.

MicroBlaze AXI4-Lite Custom Adder on Arty A7-100T using Xilinx Vivado & Vitis