Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.

The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configurations are capable of booting Linux.

🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

SERV - The SErial RISC-V CPU

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

RISC-V CPU Core (RV32IM)

Haskell to VHDL/Verilog/SystemVerilog compiler

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

Berkeley's Spatial Array Generator

32-bit Superscalar RISC-V CPU

Modular hardware build system

RISC-V XV6/Linux SoC, marchID: 0x2b

Digital Signature Service : creation, extension and validation of advanced electronic signatures

RISC-V Cores, SoC platforms and SoCs

Various HDL (Verilog) IP Cores

VUnit is a unit testing framework for VHDL/SystemVerilog

The PoC Library has been forked to github.com/VHDL/PoC. See new address below

collection of works aiming at reducing model sizes or the ASIC/FPGA accelerator for machine learning

The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core

PDK for GlobalFoundries' 180nm MCU bulk process technology (GF180MCU).

Code generation tool for control and status registers

A huge VHDL library for FPGA and digital ASIC development

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.

Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy

Open source machine learning accelerators

Allo Accelerator Design and Programming Framework (PLDI'24)

Awesome ASIC design verification

IC implementation of Systolic Array for TPU

The next generation of OpenLane, rewritten from scratch with a modular architecture