This Repository contains the Implementation of the AMBA APB4 Protocol with Verilog, featuring an APB master, APB slave with cache memory, and comprehensive testbenches. Includes scripts for fast simulation and synthesis using QuestaSim, Vivado and Quartus Prime

This project is focused on the design and verification of digital logic circuits, particularly targeting chip design using Verilog, SystemVerilog, and SVA. The main objectives included designing modules compliant with industry standards such as APB (Advanced Peripheral Bus), memory systems, and systolic matrix multiplication.

This site is hopefully a springboard for others to learn about coding in System Verilog and experimenting with FPGAs.

Design of a system bus architecture - Team Project @ ENTC UoM

Design and verification of the Advanced Peripheral Bus (APB) protocol using Verilog. Includes Verilog modules for APB operations and a testbench for verifying functionality and compliance with protocol standards.

SymbiYosys (sby) Formal Verification

Advanced Pheripheral Bus design using verilog HDL

This repo will contain the Verilog code implementation of various protocols that fall within AMBA protocol family such as APB, AHB, AXI and so on. I will implement it in parallel with learning theory. If possible I will also use UVM and system verilog to verify the functionality of the code once I finish learning system verilog and concepts of uvm

APB RAM RTL design with full UVM-based verification using constrained-random testing.

RTL implementation of GPIO core compatabile AMBA APB v3 protocol

Smart Farm Sensor System with AMBA APB Interface my RISC-V

Designed and implemented an AMBA AHB to APB Bridge which is a vital component in many SoC design enable communication between AHB and APB peripherals handling read and write transfer. Verified functionality through Verilog.

Flexible Memory Controller To APB3 Bridge