A modern hardware definition language and toolchain based on Python

Maia SDR is an open-source FPGA-based SDR project focusing on the ADALM Pluto

Board definitions for Amaranth HDL

Create fast and efficient standard cell based adders, multipliers and multiply-adders.

assorted library of utility cores for amaranth HDL

System on Chip toolkit for Amaranth HDL

An experiment for building gateware for the axiom micro / beta using amaranth-hdl

VS Code based debugger for hardware designs in Amaranth or Verilog

RISC-V CPU implementation in Amaranth HDL (aka nMigen)

Industry standard I/O for Amaranth HDL

Amaranth HDL framework for laser scanner with motion control

HDL development environment on Nix.

Playground for experimenting with and sharing short Amaranth programs on the web

RFCs for changes to the Amaranth language and standard components

command line tool for frequent amaranth HDL tasks (generate sources, show design)

W65C816-based single board computer

Experimental USB2 HS/FS host primitives for FPGAs.

RISC-V processor implemented in Amaranth

SH1107 OLED (I²C) driver, plus virtual hardware testbench.

ChaCha stream cipher modules written in Python, described using Amaranth.

Gowin platform for Amaranth-HDL

My collection of reusable code written using the amaranth hdl

A simple RISC V core written in Amaranth

A simple project template for Amaranth HDL

Bonsai is a RISC-V CPU designed using Amaranth HDL. (wip)

This repository contains MCH2022 badge examples for Amaranth HDL.

Various FPGA Amaranth projects

Examples for the Chubby Hat FPGA Development platform