Introduction

A block diagram level simulator for Capsim® was written in C which allows for very fast simulations and the verification of PLL performance. The Block Diagram Simulation is derived from a Capsim® phase-frequency detector and charge pump block developed by the Professor Sasan Ardalan's Ph.D. Student, Ray Kassel in 1990 at NC State University. See the Application note

The objective is to match the nonlinear mixed analog/digital PLL circuit performance with high level fast "C" modeling of the charge pump PLL.

A charge pump “C” Code Block for Capsim simulation has been written based on the formulas for the solution of the charge pump equations presented in Hanumolu, et. al [1]. The results show excellent correspondence with a Spice model. The differential equations were solved using State Space methods in [1] and accurately capture the initial conditions. A Capsim® block has been developed called CHPStateSpace based on the approach in [1]. It has been successfully used to model a charge pump PLL. Note the Capsim® High Level Model of the PLL can be used prior to Spice simulations to speed up design and optimization.

High Level Block Diagram of Charge Pump PLL Synthesizer

The Charge Pump PLL Capsim® Block Diagram System can be used to perform simulations for trade offs in PLL design parameters as well as investigations into stable and unstable conditions.

A detailed paper has been written describing the theory and modeling used in the Capsim® simulation modeling. Check the link .

References

[1] Hanumolu, P.K.; Brownlee, M.; Mayaram, K.; Un-Ku Moon,“Analysis of charge pump phase-locked loops”, Circuits and Systems I: Regular Papers, IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, Volume 51, Issue 9,Date: Sept. 2004, Pages: 1665 – 1674

[2] Ray Kassel, Sasan Ardalan,"Clock Recovery from Phase Encoded Data: Capsim Application Note", North Carolina State University, Center for Communications and Signal Processing (CCSP), December 1991.

Note on Capsim® Graphical Interface

Note this repository supports the Text Mode Kernel version of Capsim®. The graphical block diagram is from the soon to be released Capsim® Version 7 which uses Qt® for interactive graphical interface. However, the topology in this Repository are the same. You can use the block names in the screen shot and then use the Capsim® command "to blockname" to go the the block, change parameters and run the simulation. There is a lot of benefit to the non-graphical mode in portability and flexibility. The graphical version also supports the text mode operation.

An updated link to Capsim® Version 7 using Qt® will be provided in the Repository on GitHub. Stay tuned.

Capsim® Charge Pump PLL Synthesizer Block Diagram, VCO 1 GHz, Divide by N (DBN) N=8, Reference Clock 125 MHz

Capsim® Phase Frequency Detector Hierarchical Block Diagram

Plots of VCO Input Signal for VCO Center Frequencies of 1.1 GHz and 1.01 GHz Showing Convergence to 1 GHz (8*125 MHz)

Plot of Reference Clock and DBN (Divide by N, N=8) Showing Phase and Frequency Alignment

Zoomed In Plot Initial Reference Clock and DBN (Divide by N, N=8)

Zoomed In Plot Final Reference Clock and DBN (Divide by N, N=8) Showing Phase and Frequency Alignment

Plot of Jitter Between Reference Clock at 125 MHz and DBN N=8 Signal Showing Convergence

Block Digram for Jitter Measurement (Reference Clock and DBN Read from File)

List of Topologies (Block Diagrams and Hierarchical Blocks)

Item	Topology Name	Description	Author	Date
1	pll_chp.t	Charge Pump PLL Synthesizer Using the Charge Pump State Space Model and Phase Detector Hierarchical Block. See screen shot here. In the topology N=8, the reference clock is 125 MHz, and the VCO center frequency is 1 GHz. The sampling rate is 10**12 Hz or 1ps time interval. The VCO center frequency can be changed as well as the Divide by N (DBN) parameter N to synthesize different signals ( buffered VCO which will be N*125MHz). The synthesizer will work with different VCO center frequencies ( for example 1.1GHz or 1.01 GHz) and produce a VCO output of N*125MHz working for cases when the VCO is obviously not exactly 1 GHz. Many other parameters can be changed, especially, in the Charge Pump Block (CHPStateSpace).	Ardalan and Kassel	1991-2018
2	phasedet.t	Phase Detector Hierarchical Block Implemented With Capsim® Logical Blocks. For screen shot see here.	Ray Kassel	1991
3	jitter.t	Topology used to compute the jitter using the reference clock and the Divide by N (DBN) block output. The file "jitter,tim" is created which can be plotted using the IIPPlot Java Application. Note the files ref.dat and dbn.dat are read. These are created when simulating the topology pll_chp.t .	Pryson Pate	1988

List of Blocks

Item	Block Name	Description	Author	Date
1	CHPStateSpace.s	Charge Pump. Reference for State Space Approach: Hanumolu, P.K.; Brownlee, M.; Mayaram, K.; Un-Ku Moon, “Analysis of charge-pump phase-locked loops”, Circuits and Systems I: Regular Papers, IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, Volume 51, Issue 9, Date: Sept. 2004, Pages: 1665 – 1674. See PLL Analysis paper .	Ardalan	2007
2	DBN.s	Divides input clock frequency by parameter N	Ardalan	2007
3	VCO.s	voltage-controlled multivibrator parameters: fs, sampling frequency fo, center frequency inputs: lambda, phase update term output: square wave equivalent of cos(2*PI*fo*t+theta) description: This block produces samples of the outputs every 1/fs seconds with frequency of fo. The phase is updated as theta=theta+lambda (integrates the input)	Kassel and Ardalan	1991
4	jitter.s	This block finds the relative phase of a signal to a reference. One parameter specifies the trigger edge (true for rising, false for falling). The other specifies the output rate (synchronous or one per cycle). The output is the phase difference of the chosen edges in degrees. The phase is found from a linear interpolation of the values on either side of a zero crossing.	Pryason Pate	February 2, 1988
5	pulse.s	Generates Pulse Train. The following parameters specify the pulse delay, width and period: np=period in samples nw=pulse width in samples nd=delay in samples	Ardalan	November 1987

Instructions for Running Capsim® Charge Pump PLL Block Diagram Simulation.

Obtain the Capsim® Text Mode Kernel (CapsimTMK) for Linux from:

GitHub Capsim Text Mode Repository

CapsimTMK is distributed with hundreds of blocks.

When you download the GitHub charge-pump-pll Repository, there will be a folder called CAPSIM. In this folder are all the blocks and topologies (block diagrams) that you will need to model and simulate the charge pump pll. The BLOCKS folder contains the blocks CHPStateSpace.s, DBN.s and VCO.s . The TOPS directory contains the topologies, in particular pll_chp.t .

To build capsim, start up a terminal session in Linux and change directory to the charge-pump-pll/CAPSIM directory. In this directory there is a Makefile. Execute the command make in the terminal. The capsim executable will be created. Note that the CAPSIM path should be setup pointing to the capsim-tmk installation.

Running the Simulations

Once capsim has been built, change directories to the TOPS directory. From there type:

../capsim pll_chp.t

The following will be displayed on the terminal:

--/charge-pump-pll/CAPSIM/TOPS$ ../capsim pll_chp.t
Welcome to Capsim Text Mode Kernel (CapsimTMK)
(c)1989-2017 Silicon DSP Corporation
This is free software; see the source for copying conditions. There is NO
warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
http://www.silicondsp.com
Version 6.2
Running topology pll_chp.t
model name: pll_chp
plot created file: Ref_Clock.tim 
plot created file: UP.tim 
plot created file: DOWN.tim 
plot created file: VCO_In.tim 
plot created file: VCO.tim 
plot created file: PLL_FB.tim 

The simulation of the topology pll_chp.t will also create two files ref.dat and dbn.dat .

These two files will be used by the jitter.t topology to compute the pll jitter.

For now lets plot some results.

Type the following in the terminal:

java -jar $CAPSIM/TOOLS/IIPPlot.jar VCO_In.tim

This will produce a plot of the input signal to the VCO. This will show the pll converging. Here is an example with the VCO set to 1.0 GHz.

Be patient with the plot as the data set is very large.

Note that X Axis has been set to fixed point and the theme changed.

For documentation on IIPPlot see this link.

To obtain the jitter run the following:

../capsim jitter.t

The file jitter.tim will be created. Plot it with the following command:

java -jar $CAPSIM/TOOLS/IIPPlot.jar jitter.tim

Below is a plot of the jitter. Note that the Y axis is in degrees and has been set to show fixed point labels.

Linux Tux By Larry Ewing, Simon Budig, Garrett LeSage - https://isc.tamu.edu/~lewing/linux/, http://www.home.unix-ag.org/simon/penguin/, garrett/Tux on GitHub, CC0, Link

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