GitHunt
SA

sarmadgulzar/serial-protocols-verilog

Verilog implementations of serial communication protocols on Alchitry Cu FPGA Board

Serial Protocols Verilog

FPGA development repository for serial protocol implementations using apio and uv.

Prerequisites

  • Python with uv package manager
  • apio (installed via uv)

Usage

Build the current directory

make build

Work with a specific project

make build PROJ=example
make upload PROJ=example
make verify PROJ=example
make sim PROJ=example

Create a new project

make init PROJ=myproject

Available commands

  • make build - Synthesize the Verilog code
  • make upload - Upload to Alchitry Cu FPGA board
  • make verify - Verify the design
  • make sim - Run simulation
  • make clean - Clean build artifacts
  • make init PROJ=name - Initialize new project

All commands support the PROJ parameter to target specific project directories. Without it, commands operate on the current directory.

Languages

Verilog56.1%Makefile43.9%

Contributors

MIT License
Created September 13, 2025
Updated September 13, 2025
sarmadgulzar/serial-protocols-verilog | GitHunt