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Ronsor/riscv-zig

A RISC-V emulator written in Zig

RV64IM emulator

This repository contains a library for emulating RISC-V 64 CPUs with the multiply extension.

Caveat emptor: The implementation of RISC-V contained herein has not been tested for compliance.
It may produce incorrect results, and it most certainly does not reject all invalid instructions.

(C) 2021 Ronsor Labs.

TODO

  • Support RV32 too (should be easy)
  • Implemented privileged instructions
  • Better documentation

Languages

Zig96.4%C3.3%Shell0.2%Assembly0.1%

Contributors

MIT License
Created March 9, 2021
Updated February 23, 2026
Ronsor/riscv-zig | GitHunt