BR
BrutalSimplicity/VHDL-Multiplier-Divider
A Basic Multiplier and Divider written in VHDL (with adder/subtracter and shfiter)
This is a VHDL implementation of a Divider and Multiplier with testbenches and waveform results.
The project was completed as apart of a final semester project. The project was completed using Altera and Modelsim.
