Anjanamb/Sequential-Logic-Datasets-with-Designs
Collection of datasets and design files for sequential digital circuits, used to train and evaluate neural networks that duplicate circuit functionality.
Sequential Logic Datasets with Designs
Collection of datasets and design files for sequential digital circuits, used to train and evaluate neural networks that duplicate circuit functionality.
Table of contents
- Overview
- Quickstart
- Repository contents
- Dataset format
- How to generate new datasets
- Usage with main project
- License
- Contact / Acknowledgements
Overview
This repository contains sequential logic designs (VHDL and Quartus schematic files), testbenches, and corresponding datasets of input/output traces. These datasets are used by the companion project Digital-IC-Functionality-Duplication-Using-NN to train neural-network models that approximate digital circuit behavior.
Quickstart
- Clone the repository:
git clone https://github.com/Anjanamb/Sequential-Logic-Datasets-with-Designs.git
cd Sequential-Logic-Datasets-with-Designs-
Browse the available circuit designs and their corresponding datasets.
-
Copy the required dataset
.txtfiles into thedata/folder of the main project for training.
Repository contents
Sequential-Logic-Datasets-with-Designs/
├─ Designs/ # VHDL designs, Quartus schematic (.bdf), and testbenches (.vhd)
├─ Datasets/ # Generated input/output/state traces in text format
├─ Scripts/ # Simulation and dataset-preparation scripts
└─ README.md
- Designs/ – contains source circuit designs (flip-flops, counters, shift registers, etc.).
- Datasets/ – plain-text traces derived from testbenches (aligned inputs and outputs).
- Scripts/ – helper scripts to run simulations and extract traces.
Dataset format
Each dataset file (.txt) contains aligned columns of inputs, states, and outputs observed from the circuit simulation.
Typical format:
clk in1 in2 state out1 out2
0 0 1 00 0 1
1 1 0 01 1 0
...
- clk: clock cycle
- inX: circuit inputs
- state: encoded internal state (binary string or integer)
- outX: observed outputs
How to generate new datasets
- Modify or create a new VHDL/Quartus design in
Designs/. - Write a testbench (
.vhd) to simulate input patterns. - Run simulation in ModelSim/Quartus and export results.
- Convert the simulation output to a plain
.txttrace (using scripts inScripts/). - Place the generated dataset in
Datasets/.
Usage with main project
To use these datasets with the neural-network training project:
- Generate or select a dataset from
Datasets/. - Copy or symlink it into the
data/folder of Digital-IC-Functionality-Duplication-Using-NN. - Pass the dataset path to the training script (see main project README).
License
MIT License – feel free to use, modify, and share. Please credit the repository if used in research or academic work.
Contact / Acknowledgements
Author: Anjana Bandara (GitHub: Anjanamb)
Contributors: Ayesh-Rajakaruna, sahannt98